1. Field
This patent document relates to a semiconductor design technology, and more particularly, to a semiconductor memory device which performs a refresh operation.
2. Description of the Related Art
In general, semiconductor memory devices such as DRAM include a plurality of memory banks for storing data, and each of the memory banks includes a large number of memory cells. Each of the memory cells includes a cell transistor serving as a switch and a cell capacitor for storing data. Since current leakage occurs due to the structure of the memory cell, such as in the PN junction of the cell transistor, the data stored in the cell capacitor may be lost. Thus, semiconductor memory devices require refresh operations for recharging the memory cells before their data is lost (hereafter, referred to as ‘normal refresh operation’).
The normal refresh operation may include an auto refresh operation and a self refresh operation. The auto refresh operation refers to a mode in which the semiconductor device performs a refresh operation according to a refresh command applied from outside, and the self refresh operation refers to a mode in which the semiconductor device performs a refresh operation while sequentially changing an internal address according to a refresh command applied from outside.
Recently, in addition to the normal refresh operation, semiconductor devices have incorporated additional refresh operations on memory cells of a specific word line that is likely to lose its data due to row hammering. This operation is typically referred to as a target-row refresh (TRR) operation or a smart refresh (SR) operation.